To meet the increasing demand for high data rate communication capability, transmission systems often employ phase shift or frequency shift keying systems that are readily adapted for digital signal interfacing and processing. In quadraphase shift keyed data transmission, that are particularly useful in this regard, demodulation schemes have included the so-called Costas demodulation approach as a highly desirable technique for data recovery and signal tracking.
A basic configuration of Costas demodulator loop, such as described in U.S. Pat. No. 4,085,378 to Ryan et al., is illustrated in FIG. 1. Referring to the Figure, an incoming signal is coupled over a line 10 to one input of each of a pair of phase detectors 11 and 12. To a second input of each phase detector there is applied a carrier reference signal from a voltage controlled oscillator 22, with phase shifter 13 imparting a 90.degree. phase shift to the reference applied to detector 11. Phase detectors 11 and 12 effectively multiply the input signal by the pair of reference carriers, one of which is offset by 90.degree., or in phase quadrature, to the other by virtue of the .pi./2 phase shifter 13, to produce a pair of demodulated signals that are then coupled through low pass filters 14 and 15 (removing the double frequency component of the VCO) to provide a pair of baseband outputs representative of the signal contents of the I and Q channels. In order to provide a control reference for the VCO 22, a signal indicative of the cross talk between the channels is obtained, and the VCO is driven so as to minimize the channel cross talk, it being assumed that minimizing channel cross talk will yield the correct frequency and phase of VCO 22 for proper demodulation. For this purpose, the respective channel outputs of filters 14 and 15 are applied to one input of each of respective multipliers 17 and 19. The I and Q channel signals are also coupled through hard limiters 16 and 18 to provide sign inputs to multipliers 19 and 17, respectively. The outputs of cross channel multipliers 17 and 19 are then subtracted from one another in subtractor 20 to provide a measure of the cross talk and thereby an error signal for controlling the VCO 22. This error signal is coupled through a loop filter 21 to the control input of the VCO 22.
In order to improve upon the signal-to-noise ratio, improvements, on this basic Costas loop design have included configurations such as those described in the United States Patents to Monrolin U.S. Pat. No. 4,100,499 and Washio et al. U.S. Pat. No. 4,134,075, which are effectively decision-directed schemes. These approaches employ delays in the respective I and Q channels, whereby previous data decisions, that offer the advantage that the value of the data at its best S/N point can be utilized, are employed.
FIG. 2 shows a scheme that is basically described in the Monrolin patent involving the insertion of a delay element in the path of each channel and a sampling circuit in the cross-multiplier path. As shown in FIG. 2, a Q-channel one-half bit delay circuit 23 is coupled in the quadrature (Q) channel path between the output of filter 14 and an input of multiplier 17, and an I-channel one-half bit delay circuit is coupled in the in-phase (I) channel path between the output of filter 15 and an input of multiplier 19. Typically, the delay imparted by each delay circuit is T/2 where T is the signalling period. A pair of sampling circuits, such as D-type flip-flops 25 and 26 are coupled between limiters 16 and 18 and second inputs of multiplier 19 and 17, respectively. The clock signals for defining the signal sampling instants are supplied on line 35 from a suitable clock recovery device (not shown). Unfortunately, with this type of system, an analog delay line, such as a section of coaxial cable, is employed, so that the bandwidth of the system is limited.
In addition, due to the length of the delay line required, this type of system is impractical at all but the highest bit rates. For example, at a specific bit rate of 10 Mbps, a coaxial cable ten meters in length is required.
An improvement on the above-described delay-line implemented decision-directed scheme involves the use of sample and hold circuits in place of the delay lines themselves, as shown in FIG. 3. Namely, in place of the one-half bit delay circuits shown in FIG. 2, respective sample and hold circuits 31 and 32 are employed, with the sampling times being controlled by the recovered clock in line 30.
Now, as well as using the value of the data decision at the best signal-to-noise point, this scheme also uses the value of analog data at its best signal-to-noise point. Although this approach provides a very good S/N ratio, it suffers from the fact that very fast and accurate sample and hold circuits are necessary. Namely, the analog sample and hold circuits must store the sampled analog value of the previous bit for one bit time, then slew to a new value, e.g. from a "one" to a "zero" at the start of the next sample time. During the time that the slew is occurring a totally erroneous signal may be generated at the output of subtractor 20. In order to avoid degradation, this slew must be accomplished in a period of time that is negligible compared to the bit time, for example less than one-percent of the bit time. For the very high data rates demanded by present-day communication systems (e.g. above 50 Kbps), this approach is exceedingly difficult and complex to implement, and for higher data rates such an implementation is not feasible.